Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices
Real-time EEG classification on edge devices is bottlenecked by the floating-point arithmetic of conventional neural networks. We investigated Differentiable Logic Gate Networks (Diff-Logic) as a hardware-native alternative that compiles models into pure Boolean circuits executable via bitwise CPU operations. Through rigorous iso-parameter experiments across four EEG datasets spanning two classification tasks, binary dementia detection and 3-class emotion recognition, we compared Diff-Logic against matched-capacity Multi-Layer Perceptron (MLP) and Binarized Neural Network (BNN) baselines at fo
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- FuzzyOverlapping authors or contributors · 62%deepspeedai/DeepSpeed →
“Shared author/contributor keys: smith”
- LinkedLinked via arxiv author · 85%Shyamal Y. Dharia →
“Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices”
- LinkedLinked via arxiv author · 85%Stephen D. Smith →
“Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices”
- LinkedLinked via arxiv author · 85%Camilo E. Valderrama →
“Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices”