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  1. Home
  2. /Repositories
  3. /manjunathshiva/turboquant-mlx
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repoGitHubTrust 82 · PrimaryPublished 1mo agoLive · yesterday

manjunathshiva/turboquant-mlx

Extreme weight + KV cache compression for LLMs on Apple Silicon (MLX implementation of Google's TurboQuant)

Lineage graph

Paper → model → repo connections mined from source citations (Tier-1 exact match).

Why these links exist

Every edge carries a method, confidence, and the source snippet that justified it — so bad links are debuggable.

  • PossiblePossibly related (embedding) · 52%I mapped which local LLMs actually fit each RAM tier, 8 to 128GB (open dataset) →
  • PossiblePossibly related (embedding) · 47%OpenAI and Broadcom announce chip designed for LLM inference at scale →

Covers

newsI mapped which local LLMs actually fit each RAM tier, 8 to 128GB (open dataset)newsOpenAI and Broadcom announce chip designed for LLM inference at scale

Related across the graph

newsOpenAI and Broadcom announce chip designed for LLM inference at scalenewsI mapped which local LLMs actually fit each RAM tier, 8 to 128GB (open dataset)
Knowledge path·NOpenAI and Broadcom announce chip designed for LLM inference at scale→NI mapped which local LLMs actually fit each RAM tier, 8 to 128GB (open dataset)→Rmanjunathshiva/turboquant-mlx

Topics

apple-siliconkv-cachellmmlxquantizationturboquant

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