repoGitHubTrust 82 · PrimaryPublished 3d agoLive · 10h ago
zjunlp/LightMem
[ICLR 2026] LightMem: Lightweight and Efficient Memory-Augmented Generation
Lineage graph
Paper → model → repo connections mined from source citations (Tier-1 exact match).
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Every edge carries a method, confidence, and the source snippet that justified it — so bad links are debuggable.
- PossiblePossibly related (embedding) · 51%Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM →
- PossiblePossibly related (embedding) · 47%Anatomy of Persistent Memory's 3 Layers: Comparing ContextNest, Mem0 and Zep →
- PossiblePossibly related (embedding) · 45%Tesla V100 16GB local LLMs, single and dual NVLink benchmarks →
- PossiblePossibly related (embedding) · 48%Apple M7 Ultra Chip Planned With Up to 1.5 TB of Unified Memory →
- PossiblePossibly related (embedding) · 47%PrismML’s new Ternary Qwen3.6 27B runs near fp16 precision on 10GB of memory!!! →
Covers
newsSophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBMnewsAnatomy of Persistent Memory's 3 Layers: Comparing ContextNest, Mem0 and ZepnewsMeta fights soaring hardware costs by reusing old DDR4 server memory in new DDR5-only servers — custom CXL 2.0 chip marries legacy DDR4-2400 with cutting-edge DDR5-6400newsTesla V100 16GB local LLMs, single and dual NVLink benchmarks
Covers (incoming)
Related across the graph
newsApple M7 Ultra Chip Planned With Up to 1.5 TB of Unified MemorynewsSophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBMnewsMeta fights soaring hardware costs by reusing old DDR4 server memory in new DDR5-only servers — custom CXL 2.0 chip marries legacy DDR4-2400 with cutting-edge DDR5-6400newsAnatomy of Persistent Memory's 3 Layers: Comparing ContextNest, Mem0 and ZepnewsTesla V100 16GB local LLMs, single and dual NVLink benchmarksnewsPrismML’s new Ternary Qwen3.6 27B runs near fp16 precision on 10GB of memory!!!